This invention relates to a real-time video signal processing device comprising a real-time video signal processor for use in carrying out real-time digital video signal processing of a dynamic digital video signal. The real-time digital signal processing is typically interframe coding known in the art. THe dynamic digital video signal may represent a television signal. The video signal processor can be used as a digital filter.
A conventional video signal processor of the type described is disclosed by T. Nishitani et al, including two of the present applicants, in Proceedings of IEEE-IECEJ-ASJ International Conference of Acoustics, Speech, and Signal Proceedings, CH2243-4 (1986), pages 797-800, under the title of "Video Signal Processor Configuration by Multiprocessor Approach. "
The conventional video signal processor is for processing an input digital video signal representative of successive pictures into an output digital video signal. Each of the successive pictures is divisible into a predetermined number of blocks. The conventional video signal processor comprises a plurality of signal processing modules corresponding to the respective blocks of each picture. The signal processing modules are for processing the respective blocks of each picture into processed signals during each picture period, respectively. The picture period is 1/30 second long when the input digital video signal comprises thirty pictures per second.
Each signal processing module comprises an input memory for memorizing all data of a corresponding one of the blocks and an output memory for memorizing all data of the processed signal which is produced by the signal processing module under consideration.
Inasmuch as the conventional video signal processor can process one block of each picture during 1/30 seconds, it is possible to realize real-time processing and digital signal processing under control of software.
The conventional video signal processor is, however, defective in that it is necessary to use a memory having a large memory capacity as each of the input and the output memories when the number of the blocks for each picture is small and consequently when each block has a great amount of informations.
In order to reduce the memory capacity of each of the input and the output memories without increasing the number of the blocks for each picture, an improved video signal processor is disclosed by two of the present applicants and Takao Nishitani in Japanese in "Densi Tuusin Gakkai Sogoo Zenkoku Taikai Kooen Ronbunshuu Bunsatsu 5" (The Transactions of the National Conference of the Institute of Electronics and Communication Engineers of Japan, Division 5), published on March, 1986, page 5-150 under the title of "An Introduction of an N-line Processing to the Real-time Video Signal Processor (VSP)". For the improved video signal processor, each picture is divided into a predetermined number of principal blocks. Each principal block consists of a predetermined number n of scanning lines of the input digital video signal, where n represents a predetermined positive integer. Each principal block is divided into a preselected number m of partial blocks so that the partial blocks overlap one another at their peripheral parts, where m represents a preselected positive integer which is greater than one.
The improved video signal processor comprises a plurality of signal processing modules corresponding to the partial blocks of each principal block. Responsive to the input digital video signal, the signal processing modules are used to process the respective partial blocks of each principal block into processed signals during a time duration difined by each of the principal blocks, respectively. Thus, the improved video signal processor produces a sequence of the processed signal as an output digital video signal.
It will now be assumed that the number of the signal processing modules of the improved video signal processor is equal to that of the signal processing modules of the above-mentioned conventional video signal processor. In the improved video signal processor, the signal processing modules process the respective partial blocks each of which is smaller than each block processed by the respective signal processing modules in the conventional video signal processor. As a result, each signal processing module of the improved video signal processor may comprise input and output memories, each having a memory capacity which is smaller than that of each signal processing module of the above-mentioned conventional video signal processor.
The improved video signal processor can execute spatial filtering operation fo spatially filtering the input digital video signal to produce a spatially filtered signal as the output digital video signal. However, the improved video signal processor cannot execute interframe coding.
Description will now be made why the interframe coding cannot be executed. On executing the interframe coding, a prediction signal must be produced on frame period prior to a current input digital video signal which is subjected to the interframe coding. However, the improved video signal processor processes the input digital video signal during the time duration which is defined by each principal block and which is therefore shorter than the picture period. Thus, the prediction signal can not be obtained by the improved video signal processor without modification of the architecture of the processor. This is the reason why the improved video signal processor cannot execute the interframe coding.
Moreover, the improved video signal processor can not execute temporal filtering operation for temporally filtering the input digital video signal to produce a temporally filtered signal as the output digital video signal. This is because a feedback signal must be produced one frame period prior to a current input digital video signal subjected to the temporal filtering on executing the temporal filtering.